Multiscale Modeling of Block Polymer Assembly for Nanomanufacturing

Juan de Pablo
Seminar

Directed copolymer assembly (DCA) has emerged as a promising alternative for patterning at sub-lithographic length scales. The basic idea is to control the self-assembly of multiblock polymers through the application of external fields, surface patterns, and processing conditions. By employing materials whose characteristic dimensions are smaller than those of canonical features encountered in semiconductor devices, it is possible to integrate self-assembling systems into existing manufacturing processes, thereby increasing resolution at modest expense. Much progress has been made over the past decade, but a number of significant challenges remain. Our recent efforts at the University of Chicago have focused on development of a molecular based, multiscale computational modeling approach aimed at gaining a fundamental understanding of directed copolymer assembly on nanopatterned substrates. This presentation will begin with a brief overview of available theoretical and computational approaches, along with a discussion of their advantages and limitations. That overview will be followed with a description of recent modeling advances that have enabled quantitative descriptions of time-dependent, morphological evolution during thermal annealing and solvent annealing processes. In the latter case, the models allow for a description of the selective, time-dependent swelling (or de-swelling) of distinct domains of the copolymer resist material, and are therefore able to describe the path followed by particular blends of copolymers, homopolymers, and solvents, on their way to metastable or equilibrium assembly. Given the predictive nature of such models, some of our recent efforts have gradually focused on the coupling of molecular modeling and evolutionary optimization algorithms. Through that coupling, a new paradigm is emerging in which computations are used to identify surface patterns and block polymer formulations leading to target morphologies and circuit layouts. This presentation will include a brief description of those efforts.