Casper: An Asynchronous Progress Model for MPI RMA on Many-Core Architectures

Event Sponsor: 
Mathematics and Computing Science Seminar
Start Date: 
Apr 23 2015 - 10:30am
Building/Room: 
Building 240/Room 4301
Location: 
Argonne National Laboratory
Speaker(s): 
Min Si
Speaker(s) Title: 
Guest Graduate Student - MCS
Host: 
Antonio J. Pena and Pavan Balaji

One-sided communication semantics (also known as remote memory access or RMA) allow a process to access memory regions from other processes in distributed-memory systems. With this model, processes can move data without explicitly synchronizing with the remote target process. However, the MPI standard does not guarantee that it is asynchronous. That is, an MPI implementation might still require the remote target to make MPI calls to ensure communication progress so that any RMA operations issued on that target complete. In this talk, I will introduce Casper a process-based asynchronous progress solution for MPI one-sided communication on multicore and many-core architectures by utilizing transparent MPI call redirection through PMPI and MPI-3 shared-memory windows to map memory from multiple user processes into the address space of arbitrary number of ghost processes. The objective is to enable asynchronous progress where needed while allowing native hardware-based communication where available. I will discuss the detailed design of the proposed architecture including several techniques for maintaining correctness according to the MPI-3 standard as well as performance optimizations where possible. I will also compare the performance of Casper with that of traditional thread- and interrupt-based asynchronous progress models.

Bio:

Min Si is a third year PhD Student from The University of Tokyo (Japan), under the supervision of Prof. Reiji Suda and Prof. Yutaka Ishikawa. She also works at Argonne National Laboratory as a guest graduate student, supervised by Dr. Antonio J. Pena and Dr. Pavan Balaji. Her research interests focus on parallel programming models and communication runtime systems on many-core architectures.