FPGA Architectures and CAD Algorithms with Dynamic Power Gating Support

Event Sponsor: 
Argonne Leadership Computing Facility Seminar
Start Date: 
Aug 26 2016 - 10:30am
Building/Room: 
Building 240/Room 4301
Location: 
Argonne National Laboratory
Speaker(s): 
Assem Bsoul
Speaker(s) Title: 
IBM Canada
Host: 
Hal Finkel

A Field Programmable Gate Array (FPGA) device can be configured to implement a user-specified application. Power consumption is a concern in many FPGA systems, such as battery-powered systems or systems that harness FPGAs to accelerate computation. This talk will focus on novel FPGA architectures and CAD algorithms that enable reducing FPGA’s power by dynamic Power Gating (PG). PG enables powering down components in a device to reduce its static power consumption. Previous PG techniques for FPGAs enable powering down unused components at configuration time only. However, the benefit of this is limited by the number of unused components in a device. On the other hand, the proposed architecture enables dynamically powering down the modules in an application at run-time, based on their behavior, without the need to reconfigure the device. This can lead to significant energy savings for applications with modules that experience long idle periods.

Miscellaneous Information: 

Information: Conference room is located on the fourth floor. Go to the right after you get off of the elevator. The room will be on your left hand side.

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