In this seminar, Argonne's Connor Bohannon will share their experiences at the intersection of computer engineering, hardware design, and artificial intelligence. Bohannon's work has focused on developing FPGA-based transformer inference pipelines, evaluating floating-point libraries in Chisel, and exploring ideas for GPU acceleration for EDA tools on the Aurora supercomputer. Bohannon also co-authored “Design and Implementation of a Custom Hardware Accelerator for SZx Compression in Chipyard” (SC Workshops ’25), which presents a hardware accelerator for scientific data compression developed within the RISC-V and Chipyard ecosystem. Beyond research, I enjoy developing personal hardware and software projects that help me explore new design ideas and deepen my technical understanding. Together, these experiences reflect Bohannon's growing interest in scalable, high-performance computing and hardware-software co-design. Joining Argonne represents the next step in that journey — an opportunity to continue this research and prepare for graduate studies and a Ph.D. in Computer Engineering.