A Parallelizing Compilation Framework for a Distributed Dynamic Dataflow Computing Platform

Event Sponsor: 
Mathematics and Computer Science Division Seminar
Start Date: 
Apr 5 2017 - 10:30am
Building 240/Room 1406-1407
Argonne National Laboratory
Kavitha Madhu
Pavan Balaji

Abstract: Massively parallel SoCs have emerged as efficient solutions to meet the ever-increasing performance goals of HPC applications. REDEFINE is one such scalable MPSoC architecture that offers the flexibility of combining several coarse compute and memory units, to suit the requirements of application kernels. It realizes a distributed runtime in hardware that executes task interaction graphs of applications in a dynamic macro dataflow manner. We present a compilation framework that automatically exposes parallelism of various granularities (TLP, DLP, ILP) in applications targeting REDEFINE. Additionally, it manages the runtime via specialized instructions and manages memory explicitly. The major contributions of this work include an automatic parallelizing frontend for sequential programming languages such as C99, design of a parallel intermediate representation extending the LLVM IR, efficient task and memory management schemes and support for heterogeneity in target hardware platform.
Bio: Kavitha Madhu is currently a research scholar at CAD Laboratory, Indian Institute of Science, Bangalore. She is currently pursuing PhD under the supervision of Prof. S.K. Nandy. Kavitha received B.E from Visvervaraya Technological University in the year 2010. She worked as a software developer in SAP Labs India from 2010-12. She has also worked as a doctoral intern at Morphing Machines Pvt Ltd and has contributed to a research project exploring parallel real time systems for safety critical avionics applications with SAFRAN Electronics. Her research interests are High Performance Computing, Programming Languages, Runtime systems and Compiler Design.