Pipeline and Memory Interface Synthesis of FPGA Accelerators

Event Sponsor: 
Argonne Leadership Computing Facility Seminar
Start Date: 
Sep 30 2016 - 10:30am
Building/Room: 
Building 240/Room 4301
Location: 
Argonne National Laboratory
Speaker(s): 
Zheming Jin
Speaker(s) Title: 
National Water Center, Tuscaloosa, AL
Host: 
Hal Finkel

The talk presents interesting topics in high-level synthesis and heterogeneous computing. The first topic discusses the pipeline synthesis approach to automatic generation of bandwidth-aware and resource-constrained pipelines for the floating-point arithmetic expression in register transfer language. The second topic describes the application of the pipeline synthesis and the FPGA-based kernel acceleration on a heterogeneous computing platform, the Convey HC1. Improving the memory performance for the memory-bound kernels is important. The last topic presents the research in custom memory interface synthesis of FPGA accelerators.
 

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