Techniques for Enabling Highly Efficient Message Passing on Many-Core Architectures

Event Sponsor: 
Mathematics and Computing Science Seminar
Start Date: 
Oct 26 2015 - 10:30am
Building/Room: 
Building 240/Room 4301
Location: 
Argonne National Laboratory
Speaker(s): 
Min Si
Speaker(s) Title: 
The University of Tokyo
Host: 
Pavan Balaji

Many-core architecture provides a massively parallel environment with dozens of cores and hundreds of hardware threads. Scientific application programmers are increasingly looking at ways to utilize such large numbers of lightweight cores for various programming models. Efficiently executing these models on massively parallel many-core environments is not easy. Although several approaches have been studied to achieve better parallelism and resource sharing, many of those approaches still face communication problems that degrade performance.

In this talk, Min will focus on exploiting the capabilities of many-core architectures on widely used MPI implementations. She will discuss the communication challenges existing in popular programming models and applications, and propose two efficient strategies -- a multithreaded MPI approach and a process-based asynchronous model —- to optimize MPI communication for modern scientific applications.

Bio:
Min Si is a fourth year PhD Student from The University of Tokyo (Japan), under the supervision of Prof. Reiji Suda and Prof. Yutaka Ishikawa. She also works at Argonne National Laboratory as a guest graduate student, supervised by Dr. Pavan Balaji. Her research interests focus on parallel programming models and communication runtime systems on many-core architectures.